1. Field of the Invention
The present invention relates to a semiconductor device and the method for making the same. More specifically, the present invention relates to a interconnection structure and the method for making the same for improving electrical contact between the interconnection of a first layer and the interconnection of a second layer in a semiconductor device having multilayer interconnection structure in which a contact hole for the electrical contact between the interconnection of the first layer and the surface of the semiconductor substrate and a through hole for the electrical contact between the interconnection of the first layer and the interconnection of the second layer are formed in the same region in order to improve the degree of integration.
2. Description of the Prior Art
Recently, with the advancement of the degree of integration in a semiconductor device, the number of elements formed thereon are increase and, correspondingly, the number of interconnections are also increased to present an obstacle to the improvement in the degree of integration. In order to solve this problem, a method had been proposed in which the interconnection is formed in a multilayered structure and the contact region of the interconnection of the first layer and the semiconductor substrate and the contact region of the interconnection of the first layer and the interconnection of the overlying second layer are formed in the same region in order to decrease the area of the interconnection regions.
FIGS. 1A and 1B are cross-sectional side views schematically showing the steps of manufacturing the above described multilayered interconnection of a semiconductor device. The method for manufacturing the conventional interconnection in a semiconductor device will be hereinafter described with reference to FIGS. 1A and 1B.
To start with, description will be made with reference to FIG. 1A. An insulating film such as PSG film (phosphorous doped silicon oxide film) is formed by e.g. CVD method (chemical vapor deposition) on the entire surface of a silicon semiconductor substrate (hereinafter simply referred to as a silicon substrate) on which circuit elements etc. (not shown) are formed. Then a resist film (not shown) is applied on the entire surface of the insulating film 2, and then it is exposed and etched to be patterned into a predetermined form. A penetrating hole (hereinafter referred to as a contact hole) 10 deep enough to reach the surface of the silicon substrate 1 is formed in a predetermined region of the insulating film 2 by dry etching or wet etching using the patterned resist film (not shown) as a mask. After removing the resist film used as a mask, an aluminum film is deposited to cover the insulating film 2 and the contact hole 10 by sputtering method or the like. This aluminum film is patterned by dry etching or wet etching using a resist film (not shown) as a mask to form a first layer aluminum interconnection film 3 having a predetermined form. Then an interlayer insulating film 5 is formed over the entire exposed surface by using the CVD method. A silicon nitride film, silicon oxide film or the like may be used as the interlayer insulating film 5. A patterned resist film (not shown) is formed on the interlayer insulating film 5. Then a penetrating hole (hereinafter simply referred to as a through hole) 11 reaching the surface of the first layer aluminum interconnection film 3 is formed in a predetermined region of the interlayer insulating film 5 by dry etching or wet etching, using the patterned resist film as a mask. The through hole 11 is formed such that it overlaps with the contact hole 10 in planar layout. The through hole becomes a contact hole for making electrical contact between the first layer aluminum interconnection 3 and the second layer aluminum interconnection which in turn will be formed in the following steps.
Let us turn to FIG. 1B. An aluminum film to be the second layer interconnection film will be formed on the entire exposed surface by the sputtering method or the like. This aluminum film is patterned by dry etching or wet etching into a predetermined shape to form the second layer aluminum interconnection film 6 for electrically connecting the first layer aluminum inerconnection film 3 with other circuit elements. As shown in FIG. 1B, since the contact hole 10 and the through hole 11 are formed in the same region, the effective aspect ratio of the through hole (the ratio of the depth to the width of the through hole 11) becomes large, so that the step coverage at the through hole 11 with the second layer aluminum interconnection film 6 is not satisfactory.
In a conventional semiconductor device having multilayered interconnection structure formed in the above described manner, since the contact hole in the underlying insulating film and the through hole in the interlayer insulating film are formed in the same region, the step of the underlying insulating film is added to the step of the interlayer insulating film, enlarging the effective aspect ratio of the through hole formed in the interlayer insulating film. Thus, the step coverage of the second layer aluminum interconnection film at the through hole 11 is deteriorated as shown in FIG. 1B. Consequently, it becomes difficult to make full electrical contact of the first layer aluminum interconnection film 3 with the second layer aluminum interconnection film 6, causing a problem that poor electrical contact between the first layer aluminum interconnection 3 and the second layer aluminum interconnection 6 occurs.
On the other hand, when the interlayer insulating film 5 is made thin to minimize the effective aspect ratio of the through hole 11 at the interlayer insulating film 5 in order to prevent the above described problem, the interlayer insulating film 5 can not fully effect its function, causing another problem that sufficient electrical insulation can not be kept between the second layer aluminum interconnection film 6 and the underlying first layer aluminum interconnection film or the silicon substrate 1.
Therefore, in order to solve the above described problems, in a conventional semiconductor device having multilayered interconnection structure and therefore in the method of making the same, it is necessary to form the contact hole for the first layer aluminum interconnection and the through hole for the second layer aluminum interconnection in different regions so that they may not overlap with each other. This has been a big obstacle to the improvement in degree of integration of a semiconductor device having multilayered interconnection structure.
The metal step coverage at the contact hole and the through hole is discussed in D. Culver et al., "MODELING OF METAL STEP COVERAGE FOR MINIMUM FEATURE SIZE CONTACTS AND VIAS", IEEE 1985 V-MIC Conference CH2197-2185/0000-0399$ 01.00, pp. 399-407. This reference shows that a dominant parameter in the process variables having influence to the metal step coverage is the via and contact sidewall slope.